VTU Online Courses

Parallel Computer Architecture

@VTU COE

2.7

(3) 454 Students

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What you will learn

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With the emergence of application domains requiring large data processing as well as faster compute performance, parallel computing has become a critical component. This involves the use of multi-core processors as well as tightly integrated clusters of PCs and workstations. The most exciting development is the convergence of traditionally disparate approaches of shared memory, message passing and data driven computing onto the same platform

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Lec 1: Why do we need parallel architecture ?

Preview 15:56

Lec 2: Multicore Revolution

Preview 24:09

Lec 3: What is Parallel Architecture?

Preview 53:09

Lec 4: Performance and Benchmarking

Preview 15:57

Lec 5: Reporting Results

Preview 31:04

Lec 6: Some Laws

Preview 30:22

Lec 7: A shift from sequential to parallel

Preview 19:32

Lec 8: Programming Models

Preview 20:35

Lec 9: Shared Memory Paradigm

Preview 32:43

Lec 10: Message Passing Paradigm

Lec 13: Memory hierarchy questions (1)

Preview 23:27

Lec 14: Memory hierarchy questions (2)

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Lec 15: Six basic cache optimisations (1)

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Lec 16: Six basic cache optimisations (2)

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Lec 17: Virtual Memory (1)

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Lec 18: Virtual Memory (2)

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Lec 19: Cache Coherence Problem

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Lec 20: Concept of Serialisation

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Lec 21: Coherence related Conditions

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Lec 22: Types of Coherence Protocols (1)

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Lec 23: Types of Coherence Protocols (2)

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Lec 24: VI Protocol

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Lec 25: 3 state: MSI Protocol

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Lec 26: MESI Protocol

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Lec 27: Dragon Protocol

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Lec 28: Coherence misses

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Lec 29: Coherence misses example

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Lec 30: Correctness Requirements

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Lec 31: Single-Level caches with an Atomic Bus (1)

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Lec 32: Single-Level caches with an Atomic Bus (2)

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Lec 33: Multi-Level caches with an Atomic Bus (1)

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Lec 34: Multi-Level caches with an Atomic Bus (2)

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Lec 35: Split transaction Bus

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Lec 36: Phases in Split Transaction Bus

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Lec 37: Request table and Organization

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Lec 38: Path of a Cache Miss

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Lec 39: Multi-Level cache + Split transaction Bus

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Lec 40: Introduction to Directory Cache Coherence

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Lec 41: Basic Operation of a Directory

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Lec 42: Directory Organisations

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Lec 43: Directory Overhead Optimisations

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Lec 44: Directory Protocol optimisations

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Lec 45:Proving Correctness (1)

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Lec 46: Proving Correctness (2)

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Lec 47: SGI Origin Architecture

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Lec 48: Working of protocol

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Lec 49: Correctness Issues

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Lec 50: Sequent NUMA-Q Architecture

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Lec 51: Working of protocol(1)

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Lec 52: Working of protocol (2)

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Lec 53: Correctness and Protocol Interaction

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Lec 54: Sequential Consistency

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Lec 55: Implications of Sequential Consistency

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Lec 56: Relaxed Consistency Models (1)

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Lec 57: Relaxed Consistency Models (2)

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Lec 58: Relaxing all Orders

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Lec 59: Uninterruptible Instructions

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Lec 60: Implementation of atomic instructions

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Lec70: Other synchronisation options

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Lec 71: Interconnect Overview

Kavita Bagewadi

Lecturer 15, 29, 45 are not opening . Please resolve the problem

4 months ago

Monish Gowda D S

which courses you guys completed? can anyone tell names of those. Here some videos are not opening and most of them dont have quiz questions so. who have completed just mention the course names

4 months ago

Tejas H V

Has anyone got any quizes from this course

4 months ago