Lecture 01: Introduction

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Lecture 02: Octal and Hexadecimal Number Systems

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Lecture 03: Signed and Unsigned Binary Number Representation

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Lecture 04: Binary Addition and Subtraction

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Lecture 05: BCD and Gray Code Representations

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Lecture 06: Error Detection and Correction

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Lecture 07: Logic Gates

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Lecture 08: Logic Families to Implement Gates

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Lecture 09: Emerging Technologies (Part I)

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Lecture 10: Emerging Technologies (Part II)

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Lecture 11 : Switching Algebra

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Lecture 12 : Algebraic Manipulation

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Lecture 13 : Properties of Switching Functions

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Lecture 14 : Obtaining Canonical Representations of Functions

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Lecture 15 : Functional Completeness

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Lecture 16: Minimization Using Karnaugh Ma

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Lecture 17: Minimization Using Karnaugh Maps (Part II)

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Lecture 21: Design of Adders (Part I)

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Lecture 22: Design of Adders (Part II)

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Lecture 23: Design of Adders (Part III)

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Lecture 24: Logic Design(Part I)

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Lecture 25: Logic Design(Part II)

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Lecture 26: Logic Design(Part III)

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Lecture 27: Binary Decision Diagrams (Part I)

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Lecture 28: Binary Decision Diagrams (Part II)

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Lecture 29: Logic Design using AND-EXOR Network

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Lecture 30: Threshold Logic and Threshold Gates

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Lecture 31: Latches and Flip-Flops (Part I)

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Lecture 32: Latches and Flip-Flops (Part II)

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Lecture 33: Latches and Flip-Flops (Part III)

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Lecture 34: Clocking and Timing (Part I)

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Lecture 35: Clocking and Timing (Part II)

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Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I)

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Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II)

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Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III)

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Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV)

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Lecture 40: Minimization of Finite State Machines (Part I)

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Lecture 41: Minimization of Finite State Machines (Part II)

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Lecture 42: Design of Registers (Part I)

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Lecture 43: Design of Registers (Part II)

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Lecture 44: Design of Registers (Part III)

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Lecture 45: Design of Counters (Part I)

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Lecture 46: Design of Counters (Part II)

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Lecture 47: Digital-to-Analog Converter (Part I)

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Lecture 48: Digital-to-Analog Converter (Part II)

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Lecture 49: Analog-to-Digital Converter (Part I)

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Lecture 50: Analog-to-Digital Converter (Part II)

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Lecture 51: Analog-to-Digital Converter (Part III)

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Lecture 52: Asynchronous Sequential Circuits (Part I)

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Lecture 53: Asynchronous Sequential Circuits (Part II)

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Lecture 54: Algorithmic State Machine (ASM) Chart

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Lecture 55 : Testing of Digital Circuits

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Lecture 56 : Fault Modeling

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Lecture 57 : Test Pattern Generation

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Lecture 58 : Design for Testability

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Lecture 59 : Built-in Self-Test (Part I)

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Lecture 60 : Built-in Self-Test (Part II)

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