Lec 1: Why do we need parallel architecture ?

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Lec 2: Multicore Revolution

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Lec 3: What is Parallel Architecture?

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Lec 4: Performance and Benchmarking

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Lec 5: Reporting Results

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Lec 6: Some Laws

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Lec 7: A shift from sequential to parallel

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Lec 8: Programming Models

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Lec 9: Shared Memory Paradigm

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Lec 10: Message Passing Paradigm

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Lec 11: Examples

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Lec 12: Cache Basics

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Lec 13: Memory hierarchy questions (1)

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Lec 14: Memory hierarchy questions (2)

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Lec 15: Six basic cache optimisations (1)

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Lec 16: Six basic cache optimisations (2)

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Lec 17: Virtual Memory (1)

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Lec 18: Virtual Memory (2)

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Lec 19: Cache Coherence Problem

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Lec 20: Concept of Serialisation

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Lec 21: Coherence related Conditions

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Lec 22: Types of Coherence Protocols (1)

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Lec 23: Types of Coherence Protocols (2)

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Lec 24: VI Protocol

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Lec 25: 3 state: MSI Protocol

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Lec 26: MESI Protocol

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Lec 27: Dragon Protocol

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Lec 28: Coherence misses

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Lec 29: Coherence misses example

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Lec 30: Correctness Requirements

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Lec 31: Single-Level caches with an Atomic Bus (1)

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Lec 32: Single-Level caches with an Atomic Bus (2)

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Lec 33: Multi-Level caches with an Atomic Bus (1)

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Lec 34: Multi-Level caches with an Atomic Bus (2)

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Lec 35: Split transaction Bus

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Lec 36: Phases in Split Transaction Bus

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Lec 37: Request table and Organization

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Lec 38: Path of a Cache Miss

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Lec 39: Multi-Level cache + Split transaction Bus

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Lec 40: Introduction to Directory Cache Coherence

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Lec 41: Basic Operation of a Directory

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Lec 42: Directory Organisations

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Lec 43: Directory Overhead Optimisations

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Lec 44: Directory Protocol optimisations

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Lec 45:Proving Correctness (1)

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Lec 46: Proving Correctness (2)

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Lec 47: SGI Origin Architecture

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Lec 48: Working of protocol

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Lec 49: Correctness Issues

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Lec 50: Sequent NUMA-Q Architecture

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Lec 51: Working of protocol(1)

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Lec 52: Working of protocol (2)

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Lec 53: Correctness and Protocol Interaction

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Lec 54: Sequential Consistency

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Lec 55: Implications of Sequential Consistency

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Lec 56: Relaxed Consistency Models (1)

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Lec 57: Relaxed Consistency Models (2)

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Lec 58: Relaxing all Orders

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Lec 59: Uninterruptible Instructions

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Lec 60: Implementation of atomic instructions

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Lec70: Other synchronisation options

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Lec 71: Interconnect Overview

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Lec 72: Topologies

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Lec 73: Routing

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Lec 74: Flow Control

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