What you will learn
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None
This is a most fundamental Digital Circuit Design course for pursing a major in VLSI. We do not deal with any Verilog coding during this course and instead discuss transistor level circuit design concepts in great detail. Over learning objectives of this course are: 1. Characterize the key delay quantities of a standard cell 2. Evaluate power dissipated in a circuit (dynamic and leakage) 3. Design a circuit to perform a certain functionality with specified speed 4. Identify the critical path of a combinational circuit 5. Convert the combinational block to pipelined circuit 6. Calculate the maximum (worst case) operating frequency of the designed circuit
Introduction - Digital IC Design
Preview
29:03
Transistor - 1 - PN Junction
Preview
19:45
Transistor - 2 - MOS Capacitor Threshold Voltage
Preview
29:03
Transistor - 3 - MOS Transistor Current Expression
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17:13
Transistor- 4 - Body Effect and I-V Plots
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17:33
Transistor -5 - Short Channel Transistors - Channel Length Modulation
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18:51
Transistor- 6 - Velocity Saturation and Level-1 SPICE Model
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31:38
Transistor - 7 - Drain Induced Barrier Lowering
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15:37
Transistor - 8 - Sub-Threshold Leakage
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19:08
Transistor-9 - Substrate and Gate Leakage
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19:14
Transistor - 10 - The PMOS Transistor
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30:34
Transistor-11 - Transistor Capacitance - 1
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22:16
Transistor - 12 - Transistor Capacitance - 2
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27:01
Inverter - 1 - CMOS Inverter Construction
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24:21
Inverter - 2 - Voltage Transfer Characteristics
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20:15
Inverter - 3 - Load Line Analysis
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30:06
Inverter - 4 - Trip Point for Short Channel Device Inverter
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27:41
Inverter-5 - Trip Point for Long Channel Device Inverter
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13:11
Inverter - 6 - Noise Margin Analysis-1
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17:05
Inverter - 7 - Noise Margin Analysis-2
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18:31
Inverter-8 - Noise Margin Analysis-3
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18:08
Inverter - 9 - Noise Margin Analysis-Long Channel Device Inverter-1
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31:21
Inverter - 10 - Noise Margin Analysis-Long Channel Device Inverter-2
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11:44
Inverter - 11 - Pass Transistors
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09:39
Inverter - 12 - NMOS Transistor ON Resistance and Fall Delay
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22:03
Inverter - 13 - Elmore Delay Model
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31:55
Inverter - 14 - Inverter: Transient Response
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25:57
Inverter - 15 - Inverter: Dynamic Power
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13:05
Inverter - 16 - Inverter: Short Circuit Power
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26:28
Inverter - 17 - Inverter: Leakage Power and Transistor Stacks
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26:04
Inverter - 18 - Stacking Effect and Sleep Transistors
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23:55
Inverter - 19 - Ring Oscillators and Process Variations
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23:16
CombCkt - 1 - Implementing Any Boolean Logic Function
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24:47
CombCkt - 2 - Implementing Any Boolean Logic Function: Examples. Gate sizing
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16:14
CombCkt - 3 - Gate Sizing
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21:24
CombCkt - 4 - Logic Gate Capacitance
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25:40
CombCkt - 5 - Gate Delay
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25:33
CombCkt - 6 - Parasitic Delay
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23:32
CombCkt - 7 - Gate Delay with a Load Capacitance
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25:09
CombCkt - 8 - Logical Effort
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25:31
CombCkt - 9 - Gate Delay
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22:42
CombCkt - 10 - Path Delay Calculation and Optimization Formulation
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22:37
CombCkt - 10A - Path Delay Optimization: Intuition
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22:19
CombCkt - 10B - Path Delay Optimization: Example
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22:47
CombCkt - 11 - Buffer Insertion
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27:14
CombCkt - 12 - Input Ordering and Asymmetric Gates
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24:01
CombCkt - 13 - Skewed Gates
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24:22
CombCkt - 14 - Special Functions
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19:57
CombCkt - 15 - Pseudo NMOS Logic
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13:49
CombCkt - 16 - Pseudo NMOS Inverter
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17:23
CombCkt - 17 - Pseudo NMOS Logical Effort and CVSL
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30:10
CombCkt - 18 - Dynamic Circuits and Input Monotonicity
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22:46
CombCkt - 19 - Domino Logic and Weak Keepers
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35:53
CombCkt - 20 - Transmission Gate Logic
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16:56
CombCkt - 21 - Gate Sizing for Large Circuits
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28:49
AM - 1 - Ripple Adder Introduction
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21:06
AM - 2 - Full Adder Circuit Implementation
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28:44
AM - 3 - Full Adder Optimization
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17:42
AM - 4 - Carry Skip Adder
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27:49
AM - 5 - Carry Select Adder
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19:22
AM - 6 - Linear and Square Root Carry Select Adder
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18:22
AM - 7 - Two's Complement Arithmetic
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26:49
AM - 8 - Two's Complement Sign Extension
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20:01
AM - 9 - Array Multiplier
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18:34
AM - 10 - Array Multiplier - Timing Analysis
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19:27
AM - 11 - Carry Save Multiplier
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17:58
AM - 12 - Carry Save Multiplier - Signed Multiplication
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22:43
SeqCkt - 7 - C2MOS Flop
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41:19
SeqCkt - 8 - Flop Characterization
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14:47
SeqCkt - 9 - Max and Min Delay of Flop Based Systems
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30:58
SeqCkt - 10 - Flop Min Delay Constraint
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13:28
SeqCkt - 11 - Latch - Max and Min Delay Constraints
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41:54
SeqCkt - 12 - Latch-Timing Analysis with Skew
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38:04
SeqCkt - 13 - Time Borrowing
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15:24
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Meet Your Instructor
About Instructor
VTU is one of the largest Technological Universities in India with 24 years of Tradition of excellence in Engineering & Technical Education, Research and Innovations. It came into existence in the year 1998 to cater the needs of Indian industries for trained technical manpower with practical experience and sound theoretical knowledge.
Free
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Course Duration33 h 56 m 23 s
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Course LevelIntermediate
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Student Enrolled0
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LanguageEnglish
This Course Includes
- 33 h 56 m 23 s Video Lectures
- 2 Quizzes
- 0 Assignments
- 0 Downloadable Resources
- Full Lifetime Access
- Certificate of Completion